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INI File | 2008-04-02 | 3.6 KB | 158 lines |
- [UserMenu]
- 1=access|access+-
- 2=after|after+-
- 3=alias|alias+-
- 4=architecture|architecture+-
- 5=array|array+-
- 6=assert|assert+-
- 7=attribute|attribute+-
- 8=begin|begin+-
- 9=block|block+-
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- 11=buffer|buffer+-
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- 13=component|component+-
- 14=configuration|configuration+-
- 15=constant|constant+-
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- 26=group|group+-
- 27=guarded|guarded+-
- 28=impure|impure+-
- 29=inertial|inertial+-
- 30=inout|inout+-
- 31=label|label+-
- 32=library|library+-
- 33=linkage|linkage+-
- 34=literal|literal+-
- 35=loop|loop+-
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- 108=std_logic|std_logic+-
- 109=std_logic_vector|std_logic_vector+-
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- 120=writeline|writeline+-
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- [MultiHighlight]
- Syntax=
- File=
-
- [Comment]
- 1=***************************************************************************
- 2=
- 3=<b>Syntax: VHDL </b>
- 4=<b>Version: 0.0 </b>
- 5=<b>Date: 31.03.2008 </b>
- 6=<b>Author: n.n. from Ultraedit - see example for success </b>
- 7=
- 8=<b>source file: VHDL.txt </b>
- 9=<b>filter: ultraedit2rjedit-awk.txt </b>
- 10=<b>filter version: $Revision: 1.23 $/$Date: 2006/08/15 20:05:10 $ </b>
- 11=
- 12=<b>file extensions: VHD VHO VHDL </b>
- 13=
- 14=***************************************************************************
-
- [Sample]
- 1=LIBRARY IEEE;
- 2=USE IEEE.std_logic_1164.ALL;
- 3=
- 4=ENTITY YCbCr422ToRGB IS
- 5= GENERIC (
- 6= usePipe : boolean := FALSE;
- 7= colorBits : integer := 8
- 8= );
- 9= PORT (
- 10= clk : IN std_logic
- 11= );
- 12=END ENTITY
-
-
-